nvc.com - releases

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		Breker Verification Systems: EETimes--Design Article--Stich and ship no longer viable SOCcentral--Yes, Virginia, There Is a Stitch-and-Ship System-Level Design Community--Experts At The Table: Verification Strategies--Part 3 Chip Design--It’s Time to Redefine the EDA Acronym and Maybe DAC, Too! System-Level Design Community--Experts At The Table: Verification Strategies--Part 2 EDACafe--Real Talk--SoC Verification Can be Cold as Ice System-Level Design Community--Experts At The Table: Verification Strategies--Part 1 EETimes--Blog---SoC verification is growing up fast Electronic Design--Sizing Up The Verification Problem Electronic Engineering Journal--Emulation Urge? Don't Give Up on Simulation Yet! EETimes-Verification is the Key Entrepreneurial Opportunity Electronic Engineering Journal--Breker Tests Multicore Low-Power Design--Five Verification Steps to Low-Power Success Electronic Design--What's the Deal with SoC Verification? EETimes--EDA DesignLine Blog---EDA Countdown: top three EETimes--Blog---Biz Strategy Beyond Gates & Jobs SOCcentral--Use the Power of Your SoC to Verify Its Low-Power Design Features EETimes--The forgotten SoC verification team EETimes--Character traits of a CEO EETimes--Bootstrapping as a business strategy EETimes--EDA DesignLine Blog---EDA/IP Weekly Roundup--July 18 EETimes--3-D IC implications for verification GSA Forum--Home: Solving Verification Issues Facing Semiconductor Companies Pressured to Get Products to Market EETimes--Enough of the sideshows--it's time for some real advancement in functional verification! Carbon: EDACafe--Blog--Carbon, An Essential Element of the Design Flow EETimes--Design Article---Virtual prototyping methodology to boot Linux on the ARM Cortex A15 EDACafe--What Would Joe Do?--Carbon's Hal Conklin: A conversational random walk EETimes--EDA DesignLine Blog---A look back on 2012: Business sucessses EETimes--Prototyping your way to shorter design cycles Electronic Engineering Journal--Magic, Mobile and More EETimes--Commentary--Strategic investments, partnerships drive EDA innovation Tech Design Forum--Virtual prototyping moves further into the mainstream EDACafe--Carbon Design Systems: a strategic investment from Samsung Gabe on EDA--Samsung Invests $4 million in Carbon Design Systems CEDA: SemiWiki--ICCAD at 30: Alberto Looks Back and Forward Cadence Community Blog--Alberto Sangiovanni-Vincentelli at ICCAD: From Early EDA to the "Sensory Swarm" EDACafe--IEEE CEDA Corner--CEDA to Present Luca Carloni with Early Career Award, Joel Phillips with Outstanding Service Contribution Award During ICCAD" EVE: Gabe on EDA--EVE Unveils Wireless SoC Accelerated Validation Platforms EETimes--EDA DesignLine Blog---EDA/IP Weekly Roundup--September 19th Gabe on EDA--Supporting the Community EETimes--EDA DesignLine Blog---EDA/IP Weekly Roundup--July 18th Gabe on EDA--SoC Verification Made Easy SOCcentral--Power Is on Everybody's Mind Forte Design Systems: EETimes--DesignLine Blog: EDA/IP Weekly Roundup--May 15, 2013 Tech Design Forum--Forte Cynthesizer aims at performance, power and ease of use SOCcentral--So, Just What Is ESL? EETimes--EDA DesignLine Blog---A look back on 2012: Business sucessses Electronic Engineering Journal--Priming The Pump--SystemC, Advanced Verification, and Vehicular Wi-Fi Electronic Design--Implement Abstraction By Encapsulation In SystemC EETimes--Control dominated design Kilopass: EDACafe--SIP: And in other news... Chip Design--What's Driving the Expanding Market for Silicon IP? Designing the Tehuti Networks 10GbE controller GSA Forum--Working Toward a Truly Borderless Semiconductor Business Gabe on EDA--Kilopass XPM IP Provides Non Volatile Memory in IBM 65nm LPE Process Electronic Engineering Journal--Thanks Four the Memories Gabe on EDA--Kilopass Next-Generation Gusto-2 Targets Intant-On Mobile Devices EETimes--OEMs and semiconductor suppliers take turns driving innovation and integration Gabe on EDA--Kilopass Close to Quadrupling Memory Capacity for Embedding Non-Volatile Data in SoCs EETimes--Kilopass details smaller memory footprint bit cell EETimes--Opinion: Security is the Achilles heel Gabe on EDA--Kilopass Expands XPM Non-Volatile Memory IP Enablement for Power Management EETimes--DesignLine Blog: EDA/IP Weekly Roundup--August 8th Gabe on EDA--Kilopass XPM Memory IP Adds Programmability to Javelin Products Nanette V. Collins: EDACafe--2013 recipient of the Marie R. Pistilli Women in EDA Achievement Award Design Automation Conference--My DAC Moment: 50 Years of Memories--Nanette Collins' Moment Bryon Moyer--The Company is the Channel EETimes--Opinion: Relationships matter Electronic Engineering Journal--Modern Launch--Executing a 21st-Century Technology Launch Gabe on EDA--EDA And The Tale Of A Yoga School Oasys Design Systems: EDACafe--Morning at the Oasys OneSpin Solutions: EETimes--EE Life Blog---EDA in the Cloud: OneSpin says your design is secure DeepChip--Subject: News & Rumors on TSMC CoWaS, IJTAG, OneSpin, ARM, KiloPass, Pulsic System-Level Design Community--Experts At The Table: Verification Strategies--Part 3 EETimes--EDA DesignLine Blog---What is an EDA startup? EDACafe--Hot Startups... System-Level Design Community--Experts At The Table: Verification Strategies--Part 2 SemiWiki--Integrating Formal Verification into Synthesis EETimes--EDA DesignLine Blog---Executive Focus: OneSpin CEO Brinkman System-Level Design Community--Experts At The Table: Verification Strategies--Part 1 EETimes--EDA DesignLine Blog---EDA/IP weekly roundup-–February 27th 2013 EETimes--EDA DesignLine Blog---EDA/IP weekly roundup-–February 13th 2013 Gabe on EDA--Assembling the Future: Newsletter February 2013-Verified Beyond Doubt EETimes--EDA DesignLine Blog---A look back on 2012: Business sucessses Oski: EETimes--EDA Designline Blog--Oski sponsors hardware model checking award EETimes--EDA Designline Blog--The Oski 72 hour challenge ProPlus Design Solutions: EDN--1/f noise system integrates dynamic signal analyzer Electronic Engineering Journal--Editors' Blog--Parallel Accurate SPICE Chip Design--Giga-Scale Parallel SPICE---Taking Parallel SPICE Capacity to the Next Level Tech Design Forum--ProPlus enters simulation with turbo-charged parallel SPICE Solid State Technology--ProPlus Design Solutions launches SPICE simulator for giga-scale simulations Electronic Engineering Journal--ProPlus Design Solutions Unveils Next-Generation Pure SPICE Simulator for Giga-Scale Simulations Solid State Technology--Opinion: Managing process variations Chip Design--SPICE Models No Longer Only A Foundry's Worry GSA Forum--China's Semiconductor Industry Continues to be a Bright Spot in the Global Economy Solid State Technology--NanoYield: new design for yield software released EDACafe--ProPlus: DFY solution unveiled Gabe on EDA--Assembling the Future: Newsletter November 2012-From GSDII to Good Silicon: Integrated Yield Analysis Tools are Key EETimes--EDA Designline Blog--Startup Profile: ProPlus Design Solutions Uniquify: EETimes--EE Life Blog---Adaptive IP is the wave of the future Designing the Tehuti Networks 10GbE controller EDACafe--IP Showcase--Using SIP: How they know what they know Embedded Computing Design--Pixelworks Selects Uniquify's DDR Memory Controller Subsystem IP for System Performance, Field Reliability in Its 4Kx2K Ultra High Definition TVs, Digital Projector Solutions Embedded Computing Design--Uniquify to Explore DDR Memory System Design Trends, Challenges, Solutions During "DDR with Confidence" Technology Symposium February 7 Embedded Computing Design--Uniquify to Display Adaptive, High-Performance DDR Memory Controller Subsystem IP at DesignCon EETimes--EDA DesignLine Blog---A look back on 2012: Business sucessses EETimes--EE Life--Shaking up the design services market a la Amazon Embedded Computing Design--What designers can expect with DDR4 SDRAM EDACafe--A Visit to Uniquify--Unique and Impressive Electronic Engineering Journal--The Delicate Divide Between Dreams and Reality Electronic Engineering Journal--Keeping DDR Performance Fresh DeepChip--My Cheesy Must See List for DAC 2012 EETimes--Blog--Gearing Up for DAC--IP, Flows and Services EETimes--Product Brief--Self-calibrating logic IP for DDR addresses dynamic variation EDACafe--Uniquify: The Vision is crystal clear Gabe on EDA--DAC Offers Visibility and Priceless Opportunities Vennsa Technologies: EETimes--Blog--CEO and Professor Spotlight: Andreas Veneris Electronic Engineering Journal--Working Forward Verific Design Automation: EDACafe--Entrepreneurship is Alive and Well in Our Industry EDACafe--What Would Joe Do?--Verific Design Automation: Standing tall EETimes--EDA DesignLine Blog--A unique EDA Company: Verific		Color
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Color	"I have worked with the delightful Nanette Collins for more than six years, spanning three companies. Nanette is the ultimate in a proactive PR professional (sometimes I think that I work for her!). We never worry about anything slipping through the cracks, her follow-up is as complete as it gets." Steve Carlson, Group Director, R & D Cadence Design Systems			Color