Color
Color Color Color

Breker Verification Systems:

System Design Engineering Community--Internet of Things (IoT) and EDA

EETimes--Blog---Watching the Hardware Emulation Market Take Off

EETimes--Blog---A Startup Needs a Good Board of Directors

Semiconductor Engineering--EDA Shapes Its Future

Semiconductor Engineering--Big Shift In SoC Verification

Semiconductor Engineering--EDA Hungers For Growth

Semiconductor Engineering--10 Must Knows About Virtual Prototypes

EETimes--Blog---Startup 101: Why Proxies & Mentors Matter

Electronic Engineering Journal--Adventures in Verification land: Rolling the Dice and Spinning the Wheel

Semiconductor Engineering--Do Chips Really Work The First Time?

System Design Engineering Community--Verification Management

Semiconductor Engineering--The Road Ahead For 2014: Tools

EETimes--Blog---Why Hi-Tech Startups Should Care About Culture

Electronic Design--The Verification Flow Can Enable Horizontal Reuse

Chip Design--EDA Industry Predictions for 2014--Part 2

EETimes--Blog---Hiring the Right Team

Electronic Design--Interview: Adnan Hamid Addresses Trends in Chip Verification

EETimes--Blog---Earth to EE CEOs: Know When to Delegate

SOCcentral--Threading the Way through SoC verification

Electronic Design--Remove the Processor Dilemma From Constrained-Random Verification

EETimes--Blog---It Takes a Village to Make an Entrepreneurial CEO

System-Level Design System Engineering--SoC verification is unified across simulation through to validation

Embedded Computing Design--Hitting the wall in FPGA SoC verification

Electronic Engineering Journal--Breker Supplements Simulation

Tech Design Forum--Think like designers to fill the SoC verification gap

EETimes--Blog--Launching the Product

Electronic Design--One Verification Model To Drive Them All

GSA Forum--More than Moore and the Verification Moor

EETimes--Blog--What Venture Capitalists Want: Engineer's Guide to Researching Business Opportunities

Electronic Engineering Journal--Avoiding the SoC Verification Iceberg

Electronic Engineering Journal--Software Is In Style: New C-Level SoC Verification Options

EETimes--Blog--Improving the EDA Funding Environment

Electronic Engineering Journal--A Tiny Pocket of Space--The Science of a Miniscule Sample

EDACafe--Breker Celebrates 10-year Anniversary at 50th DAC

Electronic Design--Surveying The Verification Landscape


Carbon:

Semiconductor Engineering--The Road Ahead For 2014: Tools

Semiconductor Engineering--Raising The IP Abstraction Level

Chip Design--EDA Industry Predictions for 2014--Part 2

WBJournal--Carbon Design Partners With San Jose IP Firm

Chip Design--Where is the Red Button? What is the current state of ESL Tools?

Embedded Computing Design--Expert Panel: Is EDA as easy as 1, 2, 3 these days?

EDACafe--Blog--Carbon, An Essential Element of the Design Flow


Forte Design Systems:

Semiconductor Engineering--High Level Synthesis Grows Up

Semiconductor Engineering--The Road Ahead For 2014: Tools

Chip Design--EDA Industry Predictions for 2014--Part 2

Tech Design Forum--How high-vevel synthesis helps opimize low power designs--Part 2

Electronics360--The Cost of Escalating R&D

Semiconductor Engineering--Will History Repeat Itself? Is high-level synthesis really a disruptive technology? The jury is out.

EETimes--DesignLines SoC Blog: EDA Tool Chain Too Complex

Tech Design Forum--How high-vevel synthesis helps opimize low power designs--Part 1

Chip Design--Where is the Red Button? What is the current state of ESL Tools?

Electronic Design--Interview: Forte's John Sanguinetti Tackles Trends In SoC Synthesis

Embedded Computing Design--Expert Panel: Is EDA as easy as 1, 2, 3 these days?

Electronic Engineering Journal--Editor's Blog--SystemC HLS Optimizes Power

SOCcentral--Reducing Power by Raising the Level of Abstraction

EDACafe--Patience and Fortitude Pay Off for Forte

EETimes--DesignLine Blog: EDA/IP Weekly Roundup--May 15, 2013

Tech Design Forum--Forte Cynthesizer aims at performance, power and ease of use


ICScape:

Tech Design Forum--Better management of timing closure and optimization


Kilopass:

EDACafe--Memory Pill: Kilopass Boundless Freedom to Embed

EETimes--Blog---Smart TV Will Win From TV Market Disruptions

EETimes--Blog---Semiconductor Ecosystem Tangles Into Sparse Matrix

EET ASIA--SoC design sucess hinges on IP passing JEDEC tests

Electronic Design--Interview: Harry Luan Addresses SoC Design Challenges

Chip Design--The Internet of Things Blog--How the smart phone is driving the Internet-of-things

GSA Forum--Roles of CMOS and MEMS in the Expanding Internet of Things Market

EETimes--Blog---Semiconductor industry strengths and weaknesses in Asia Pacific region

EDACafe--SIP: And in other news...

Chip Design--What's Driving the Expanding Market for Silicon IP?


Lauro Rizzatti, Verification Consultant:

EETimes--Blog---The Future of Hardware Emulation

Electronic Design--What's The Difference Between FPGA And Custom Silicon Emulators?


Nanette V. Collins:

Electronic Engineering Journal--Marketing Insider--Lessons Learned: PR and Journalism

EDACafe--2013 recipient of the Marie R. Pistilli Women in EDA Achievement Award

Design Automation Conference--My DAC Moment: 50 Years of Memories--Nanette Collins' Moment

Bryon Moyer--The Company is the Channel

EETimes--Opinion: Relationships matter

Electronic Engineering Journal--Modern Launch--Executing a 21st-Century Technology Launch


OneSpin Solutions:

EETimes--Blog---loT: A Return to Our Favorite EDA Requirements

Semiconductor Engineering--Formal Is Set To Overtake Simulation

Electronic Engineering Journal--Editors' Blog--A New Coverage Concept

System Design Engineering Community--Verification Management

Electronic Design--Interview: Dr. Raik Brinkmann Comments On EDA Verification Trends

Semiconductor Engineering--The Road Ahead For 2014: Tools

EDACafe--Guest Blog: Formal Verification's Perfect Storm of Change

Tech Design Forum--Formal verification enables Agile RTL development

Chip Design--EDA Industry Predictions for 2014--Part 2

Embedded Computing Design--Verifying embedded designs with cloud computing

EETimes--News & Analysis---Cloud-Based FPGA Verificaton from OneSpin and Plunify

Semiconductor Engineering--Do Students Need More Formal Education?

EDACafe--OneSpin's Cloud vision: Knock, knock, knocking at heaven's door

Gabe on EDA--The Data Center Is Back, But In The Cloud

Semiconductor Manufacturing & Design--Should EDA Heads Be In The Cloud?

EDACafe--Guest Post: OneSpin's Successful Return to DAC

Electronic Engineering Journal--Formal in the Cloud--OneSpin's New Spin on Cloud Computing

EDACafe--OneSpin Reaches for the Cloud

EETimes--EE Life Blog---EDA in the Cloud: OneSpin says your design is secure


Oski:

System Design Engineering Community--Verification Management

Semiconductor Engineering--The Road Ahead For 2014: Tools

Chip Design--EDA Industry Predictions for 2014--Part 2

Semiconductor Engineering--Do Students Need More Formal Education?

EDACafe--What Would Joe Do?--Oski Technology: Establishing the Decoding Formal Club

Electronic Engineering Journal--Formal: It's Still Hard--Oski Discusses End-to-End Block Verification

EETimes--EDA Designline Blog--Oski sponsors hardware model checking award


ProPlus Design Solutions:

Solid State Technology--The need for high sigma yield

Solid State Technology--An era of unprecedented change

Semiconductor Engineering--The Road Ahead For 2014: Tools

Solid State Technology--Long live FinFET

Chip Design--EDA Industry Predictions for 2014--Part 2

Solid State Technology--Celebrating 20 years of BSIM3v3 SPICE models

Semiconductor Manufacturing & Design--Eliminating the Challenges of Giga-Scale Circuit Design with Nano-Scale Technologies

Semiconductor Manufacturing & Design--Experts At The Table: Design For Yield (DFY)moves close to the foundry/manufacturing side

Solid State Technology--Monte Carlo analysis has become a gamble

Solid State Technology--SPICEing up circuit design

Solid State Technology--Learning the secrets of design for yeild

EDACafe--Guest Post: A Journey from Nano-scale SPICE Modeling to Giga-Scale Simulations at DAC

EDACafe--Meet the Company that's ProPlus Design Solutions

EDN--1/f noise system integrates dynamic signal analyzer

Electronic Engineering Journal--Editors' Blog--Parallel Accurate SPICE

Chip Design--Giga-Scale Parallel SPICE---Taking Parallel SPICE Capacity to the Next Level

Tech Design Forum--ProPlus enters simulation with turbo-charged parallel SPICE

Solid State Technology--ProPlus Design Solutions launches SPICE simulator for giga-scale simulations


Uniquify:

Semiconductor Manufacturing & Design--Big sell: IP Trends and Strategies

Electronic Design--Interview: Josh Lee Addresses DDR And Self Calibrating Logic

Electronic Engineering Journal--Bitcoin Blitzkrieg: Uniquify and the Bitcoin Boom

EDACafe--Preditions 2014: Bob Smith on the watchword for the semiconductor industry

ChipEstimate.com--Game-Changing DDR Memory IP

Chip Design--Implementing a Design Management System

Chip Design--EDA Industry Predictions for 2014--Part 1

Kilopass: News & Events--The Fast, Faster, Fastest DDR Memory IP Market

Embedded Computing Design--Design management system eliminates ASIC shortcut risk

Kilopass--Memory Pill--With Rapidly Evolving Semiconductor Chip Design, Contract Engineering Prospers

EDACafe--Guest Post: A Look at DAC through Ray-Bans

EDACafe--Lifestyles: Jazz Cellars in Dogpatch

EDACafe--Uniquify, Uniquely Silicon Valley

EETimes--EE Life Blog---Adaptive IP is the wave of the future


Verific Design Automation:

Gabe on EDA--Google, TI, IBM, Synopsys, Verific, and Wearable Technology

EDACafe--What Would Joe Do?--Costello & Carlson: Buckle your seat belt...

EDACafe--What Would Joe Do?--IDAC: What EDAC might have been

EDACafe--Entrepreneurship is Alive and Well in Our Industry



Color
Color Color
Color Color Color
Color Color
Color Color
Color Color
Color Color
Color Color Color Color Color
Color
Color
Color
"I have worked with the delightful Nanette Collins for more than six years, spanning three companies. Nanette is the ultimate in a proactive PR professional (sometimes I think that I work for her!). We never worry about anything slipping through the cracks, her follow-up is as complete as it gets."

Steve Carlson, Group Director, R & D
Cadence Design Systems

Color